The present invention relates to an integrated circuit having a semiconductor arrangement, a power semiconductor component and an associated production method, and in one embodiment to a DMOS power semiconductor component with a special intermediate dielectric.
In the field of power semiconductor technology, the integration of an ion- and moisture-tight dielectric layer or of an ion- and moisture-tight intermediate dielectric in the upper region of the metallization of a semiconductor component constitutes a significant requirement.
Requirements of this type have been achieved by depositing a relatively thick passivation layer including silicon nitride, for example, or a layer sequence of silicon oxide and silicon nitride above the topmost metallization level, over the power metallization for a respective power supply, and patterning it. What is disadvantageous in this case is the formation of passivation cracks during thermal cyclic loading, such as regularly occur in particular in the case of power semiconductor components. In this case, the molding composition or potting composition exerts large mechanical stresses on the semiconductor component or chip during a temperature cycle. These forces act on the passivation, the underlying metallization layer (for example for a power supply) being plastically deformed on account of its comparatively low strength.
As a result, in particular at the edges of the metallization layer in the overlying brittle passivation layer or silicon nitride passivation, such large mechanical stresses can be produced that the passivation layer breaks. Numerous cracks arise as a result, through which mobile ions such as sodium, for example, and moisture can penetrate. The consequences are alterations of the device properties, such as, for example, threshold voltage shifts, and corrosion of the metallization layers. Furthermore, this conventional solution requires an additional photolevel for the patterning of the passivation layer, which is in turn reflected in increased costs.
As an alternative solution, in conventional semiconductor arrangements a silicon nitride layer has been integrated between an intermetal oxide and the power metallization layer. In this conventional realization, the passivation is part of the intermediate dielectric (Intermetal Dielectric, IMD), whereby one photolevel can be saved.
Furthermore, the probability of cracking is significantly reduced since the intermediate dielectric usually lies over very thin metal layers (≦1 μm), in contrast to the topmost power metallization layer thicknesses of greater than or equal to 2.5 μm. The thinner these layers, the lower their plastic deformability, for which reason cracking is inhibited. What is disadvantageous in this case, however, is that such integration of silicon nitride into the intermediate dielectric leads to gate oxide damage for which tolerance cannot be afforded particularly in the case of DMOS power semiconductor components (Diffused Metal Oxide Semiconductor) in the trenches, and to component drifts. A suspected cause in this case is the hydrogen which is incorporated in the silicon nitride layer and which can lead to severe damage to the respective semiconductor components.
Therefore, there is a need to provide a semiconductor arrangement, a power semiconductor component and an associated production method, wherein good ion- and moisture-tightness can be realized with low costs.
For these and other reasons, there is a need for the present invention.